Semiconductor technology is progressing very rapidly toward deep submicron geometries to minimize the die size and increase the circuit speed. As the geometries get to smaller dimensions, the interconnect capacitances rather than transistor switching speeds become the dominant factor limiting speed and density. In addition, the current semiconductor technology relies on high performance transistors that are arranged in 2-dimensional arrays. These transistors are fabricated in a single crystal material of silicon (Si) in order to accomplish the high mobility and low leakage current that result in good transistor threshold control, low voltage operation, high drive current, and high fan-out or gain. Also, as the critical lithography dimensions shrink the performance of the transistors laid out in a planar configuration will be limited by effects such as tunneling between gate to source and drain, and punch-through between the source and drain.
Existing polysilicon materials, generally formed from layers of amorphous silicon and annealed, are being developed to act as a switch or low performance driver for active matrix LCD displays. These devices suffer from low mobility and high leakage currents and the performances achieved with these transistors are very limited and are significantly poor compared to single crystal transistor performance.
Currently, CMOS circuits are made in a planar fashion and devices are interconnected by long metal lines (multi-layer) that run from one part of the circuit to the other on top of an isolating dielectric. Vias are used to access the devices and multi-layer metals are used to increase the connectivity of devices. With increasing density and complexity of devices, circuits, and long metal lines, it is extremely difficult to interconnect devices in the same plane. The speed of the circuit is affected (and is becoming a limiting factor in many large circuits) because of long line length of interconnects and increased RC time constant. Clock skew, signal delays, and parasitic leakage, etc. affect the performance of the circuit.
In a planar circuit lay-out, the number of input/output leads are limited. Also, larger die sizes are being limited by tool field size of such tools as steppers.
Accordingly, it would be highly desirable to provide a convenient method of producing efficient three dimensional semiconductor circuits.
It is a purpose of the present invention to provide a new and improved method of producing 3D semiconductor circuits.
It is another purpose of the present invention to provide a new and improved method of producing 3D semiconductor circuits which increases density and minimizes interconnect lengths.
It is another purpose of the present invention to provide a new and improved method of producing 3D semiconductor circuits which is convenient and easy to perform without introducing additional cost and labor.
It is still another purpose of the present invention to provide a new and improved method of producing 3D semiconductor circuits capable of producing larger and more complicated semiconductor circuits with reduced RC time constants, clock skew, signal delays, and parasitic leakage.
It is a further purpose of the present invention to provide new and improved high performance semiconductor devices with high mobility and low leakage current that result in good transistor threshold control, low voltage operation, high drive current, and high fan-out or gain.
It is a still further purpose of the present invention to provide new and improved high performance 3D semiconductor circuits which can be made more complicated and with reduced RC time constants, clock skew, signal delays, and parasitic leakage.